1. Statement of the Technical Field
The inventive arrangements relate to digital communication equipment using an error correction technique. More particularly, the inventive arrangements relate to a serial concatenated conventional code decoder.
2. Description of the Related Art
A serially concatenated convolutional code (SCCC) decoder provides a means for recovering information bits from a codeword. A codeword is often comprised of a bitstream that has been encoded using a forward error correction (FEC) technique based on at least one convolutional code. A codeword may be a relatively large sequence of information bits (for example, a few thousand information bits) to provide a high recoverability of encoded information contained therein.
One algorithm that is conventionally used in SCCC decoders for decoding coded sequences is the MAP algorithm. MAP is an acronym for the phrase “Maximum Aposteriori Probability.” The MAP algorithm provides a method for determining the most probable information bits which were transmitted based on a noisy signal received over a communication channel. It is know in the art that the MAP algorithm is an inherently Soft-Input, Soft-Output (SISO) algorithm. Soft information refers to soft-values (which are represented by soft-decision bits) that comprise information about the bits contained in a coded sequence. In particular, soft-values are values that represent the probability that a particular bit in a coded sequence is either a one (1) or a zero (0). For example, a soft-value for a particular bit can indicate that a probability of a bit being a one (1) is p(1)=0.3. Conversely, the same bit can have a probability of being a zero (0) which is p(0)=0.7. The most commonly used soft values are log-likelihood ratios (LLR's). An LLR which is a positive value suggests that the bit is most likely to be a one (1) whereas a negative LLR suggests that the value of the bit is most likely a zero (0).
It is known that soft values can be used in SCCC devices for decoding concatenated codes. In general, concatenated codes use two codes (an inner code and an outer code) with some interleaving between them. Accordingly, SCCC decoders are commonly implemented with two separate decoders that are each utilizing MAP algorithms for the decoding process. An inner decoder decodes the inner code and an outer decoder decodes the outer code. The decoders are commonly configured for operation in an iterative process where the outputs of one decoder are repeatedly communicated to the other decoder. Since the MAP algorithm is a SISO type algorithm, the soft-values (represented by soft decision bits) generated by the MAP algorithm in one decoder can be used as inputs to the MAP algorithm in the other decoder.
During a first iteration of a concatenated code, an inner decoder processes soft-value approximations to bits output from an inner encoder. As a result of this processing, the inner decoder outputs soft-value approximations to the bits that were input to the inner encoder in an encoding process. Similarly, the outer decoder uses soft-value approximations to bits output from an outer encoder. Since the bits output from the outer encoder were permuted or interleaved (as explained in the preceding paragraph), the soft-value approximations are derived by applying a reverse permutation to the soft-value approximations output from the inner decoder prior to being communicated to the outer decoder. This reverse permutation is known in the ad as depermutation. The outer decoder can produce two different outputs. One is a soft-value approximation to data that was input to the outer encoder. This data is the original, unencoded data, and is not of interest until a final iteration. This data need not be permuted or depermuted. The other output of the outer decoder is a refinement to soft-value approximations to bits output from an outer encoder. This output is interleaved (i.e., re-arranged) in the same manner as an encoder permuted output bits of the outer encoder prior to communicating the bits to the inner encoder. These permuted soft-value approximation outputs from the outer decoder approximate the bits input to the inner encoder and can therefore be used in a second iteration of the decoding process.
During the second iteration of the decoding process, the permuted soft-value approximation outputs are communicated to the inner decoder. In this regard, it should be appreciated that the inner decoder uses the permuted soft-values approximations of bits input to the inner encoder to produce refined soft-value approximations of bits input to the inner encoder. The inner decoder also uses the soft-value approximations of bits output from the inner encoder to produce refined soft-value approximations of hits input to the inner encoder.
SCCC decoders are often implemented on field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). In this regard, it should be understood that an SCCC decoder is typically designed to include an input buffer memory, a processing loop module, and an output buffer memory. The input butter memory is comprised of hardware and firmware configured to receive soft-decision bits from an external device and to temporarily store the same. The processing loop module is comprised of an inner decoder module, a depermutation buffer memory, an outer decoder module, and a permutation buffer memory. The burden of decoding information contained within a codeword is split between the inner decoder module and the outer decoder module.
The inner decoder module is comprised of hardware and firmware configured to read soft-decision bits, in a sequential or a non-sequential order, from different locations in the input buffer memory and/or the permutation module. In this regard, it should be appreciated that a non-sequential ordering of soft-decision bits causes a bottleneck or congestion of soft-decision bits at the inner decoder module. Upon receipt of the soft-decision bits, the inner decoder module begins processing the same. This processing typically involves performing a relatively simple decoding operation based on a corresponding convolutional inner code. After processing the soft-decision bits, the inner decoder module communicates the processed soft-decision bits, in a sequential or a non-sequential order, to the depermutation buffer memory for depermutation (i.e., rearrangement or reorganization) and storage. It should be understood that depermutation of soft-decision bits is necessary to reverse a permutation of soft-decision bits that occurred in an encoding process. It should also be understood that a non-sequential ordering of soft-decision bits causes a bottleneck or congestion of the soft-decision bits at the depermutation buffer memory.
The outer decoder module is comprised of hardware and firmware configured to retrieve depermuted soft-decision bits from the depermutation buffer memory. Upon receipt of soft-decision bits, the outer decoder module begins processing the received soft-decision bits. This processing typically involves performing a relatively simple decoding operation based on a corresponding convolutional outer code. After processing the soft-decision bits, the outer decoder module communicates the processed soft-decision bits, in a sequential or a non-sequential order, to the permutation buffer memory for permutation (i.e., rearrangement or reorganization) and storage. It should be understood that permutation is necessary to realign the soft-decision bits to the permutation that occurred in an encoding process. It should also be understood that a non-sequential ordering of soft-decision bits causes a bottleneck or congestion of the soft-decision bits at the permutation buffer memory. Thereafter, a sequence of permuted soft-decision bits is communicated, along with the original codeword, to the inner decoder module.
The above described process is performed for ‘M’ iterations. After ‘M’ iterations, the outer decoder module produces decoded information bits. Subsequently, the outer decoder module forwards the decoded information bits to the output buffer memory for storage.
Despite the advantages of such a conventional SCCC decoder, it suffers from certain drawbacks. For example, the above described decoding process requires a relatively large amount of time to complete. The above described decoding process also results in a bottleneck or congestion of the soft-decision bits at the inner decoder module, the depermutation buffer memory, and the permutation buffer memory. As such, there remains a need for a SCCC decoder having an improved processing time with a negligible performance loss. There also remains a need for a SCCC decoder absent of this bottleneck or congestion characteristic.